1. Field
Exemplary embodiments of the present invention relate to a method for fabricating a nonvolatile memory device, and more particularly, to a method for fabricating a nonvolatile memory device including a cell region and a peripheral circuit region having different pattern densities.
2. Description of the Related Art
A nonvolatile memory device represents a memory device that retains stored data even if the supply of power is interrupted, and for example, an NAND type flash memory device and the like have been extensively used.
A nonvolatile memory device includes a cell region and a peripheral circuit region. The cell region includes a plurality of memory cells in order to stores data. The peripheral circuit region includes a driving circuit, a voltage generation circuit and the like for the operation of the nonvolatile memory device, and various unit elements for the configuration of these circuits, for example, transistors, resistors and the like are formed therein. A method for fabricating the nonvolatile memory device will be described below.
FIGS. 1 to 4 are cross-sectional views illustrating a method for fabricating a conventional nonvolatile memory device.
Referring to FIG. 1, a cell region C and a peripheral circuit region P are defined in a substrate 100. The cell region C represents a region, where a plurality of memory cells are to be formed, and each memory cell includes a tunnel insulation layer, a floating gate, a charge blocking layer, and a control gate which are sequentially stacked on the substrate 100. A first peripheral circuit region P1 of the peripheral circuit region P represents a region where a peripheral circuit transistor is to be formed, and a gate (hereinafter, referred to as a peripheral circuit gate) of the peripheral circuit transistor is formed of substantially the same material layer as the floating gate and the control gate of the cell region C. That is, the peripheral circuit gate may include a floating gate and a control gate, which are directly coupled to each other, so that the floating gate and the control gate are electrically connected to each other. A second peripheral circuit region P2 of the peripheral circuit region P represents a region, where a resistor is to be formed, and the resistor is formed of substantially the same material layer as the floating gate of the cell region C.
A first insulation layer 110 for the tunnel insulation layer and a first conductive layer 120 for the floating gate are formed on the substrate 100.
Referring to FIG. 2, the first conductive layer 120, the first insulation layer 110, and the substrate 100 are etched using a mask pattern (not illustrated) that exposes an isolation region, so that isolation trenches and active regions A1 to A3 defined by the isolation trenches are formed in the cell region C, and the first and second peripheral circuit regions P1 and P2. The first conductive layer 120 and the first insulation layer 110 etched in the above process are indicated by reference numerals 120A and 110A, respectively.
An insulation layer is filled in the isolation trenches to form an isolation layer 130. In detail, the insulation layer with a sufficient thickness to fill the isolation trenches is formed, and a chemical mechanical polishing (CMP) process may be performed until the first conductive layer 120A is exposed, thereby forming the isolation layer 130.
Referring to FIG. 3, a mask pattern 140 covering the peripheral circuit region P is formed, and a part of the isolation layer 130 of the cell region C exposed by the mask pattern 140 is removed. A partially removed isolation layer 130 of the cell region C is indicated by reference numeral 130A. As a result of the above process, in the cell region C, the upper portion of the first conductive layer 120A protrudes from the isolation layer 130A. The reason for performing the above process is that a coupling ratio increases by increasing a contact area between the control gate and the floating gate.
Referring to FIG. 4, a second insulation layer 150 for a charge blocking layer is formed over the process resultant after the mask pattern 140 is removed, and the second insulation layer 150 has a region (hereinafter, referred to as an open region) 01 that exposes a part of the first conductive layer 120A of the first peripheral circuit region P1. The reason for forming the open region 01 is that the floating gate and the control gate of the peripheral circuit gate formed in the first peripheral circuit region P1 are prevented from being disconnected from each other by the second insulation layer 150, and the floating gate and the control gate are electrically connected to each other.
A second conductive layer 160 for a control gate is formed on the second insulation layer 150 having the open region 01.
Although not illustrated in the drawings, the first insulation layer 110A, the first conductive layer 120A, the second insulation layer 150, and the second conductive layer 160 of the cell region C are patterned, thereby forming the above-mentioned memory cells. Furthermore, the first conductive layer 120A, the second insulation layer 150 having the open region 01, and the second conductive layer 160 of the first peripheral circuit region P1 are patterned, thereby forming the above-mentioned peripheral circuit gate. Furthermore, the second conductive layer 160 of the second peripheral circuit region P2 is selectively etched, thereby forming the above-mentioned resistor formed only of the first conductive layer 120A.
However, the above-mentioned fabricating method has the following concerns.
First, in the process of FIG. 2, the isolation trench formation process and the process for forming the isolation layer 130 filled in the isolation trenches may be performed to the cell region C, the first peripheral circuit region P1, and the second peripheral circuit region P2, simultaneously. Here, the pattern density of the cell region C may be higher than that of the peripheral circuit region P. In other words, the active region A1 and the isolation layer 130 of the cell region C may be densely formed as compared with the active regions A2 and A3 and the isolation layer 130 of the peripheral circuit region P. Due to a loading effect caused by such pattern density difference, it may cause many differences between the cell region C and the peripheral circuit region P, for example, in an etching speed of the etching process performed in order to form the isolation trenches, in a filling thickness of the insulation layer filled in order to form the isolation layer 130, and in a CMP speed of the CMP process performed in order to form the isolation layer 130.
Furthermore, in the process of FIG. 3, in order to allow the first conductive layer 120A to protrude from the isolation layer 130A only in the cell region C, an additional process for forming the mask pattern 140 covering the peripheral circuit region P may be required. Since the mask pattern formation process passes through a series of steps such as photoresist coating, exposure, and development steps, the cost, time, and degree of difficulty in the total process may be increased as the number of the mask pattern formation processes may be increased.
In addition, after the isolation trenches are formed in the process of FIG. 2, an ion implantation process is further performed to the substrate 100 of the first peripheral circuit region P1 in order to improve a standby current of the peripheral circuit transistor. Such an ion implantation process is performed in the state that the mask pattern covering the cell region C and the second peripheral circuit region P2 has been formed. However, in the process for removing the mask pattern after the ion implantation process is performed, the first conductive layer 120A already formed in the cell region C may lean, which is called a leaning phenomenon. This is because the first conductive layer 120A already formed in the cell region C has a very small line width as compared with the peripheral circuit region P.
In this regard, a fabricating method of the nonvolatile memory device is being developed to address the above concerns.